summaryrefslogtreecommitdiff
path: root/kc/core/cpu/exceptions.S
diff options
context:
space:
mode:
authorAda Christine <adachristine18@gmail.com>2022-03-23 00:20:42 +0000
committerAda Christine <adachristine18@gmail.com>2022-03-23 00:20:42 +0000
commitfd0decea3bfc29523dad2b7a62526d023fe3ccc8 (patch)
tree7f3a841117a8a3f00ee8afaaf3a35ca7f864d382 /kc/core/cpu/exceptions.S
parenteb022d780afe1e5e92547b6b3c2369dde1c4cc0b (diff)
misc fixes
Diffstat (limited to 'kc/core/cpu/exceptions.S')
-rw-r--r--kc/core/cpu/exceptions.S8
1 files changed, 2 insertions, 6 deletions
diff --git a/kc/core/cpu/exceptions.S b/kc/core/cpu/exceptions.S
index 8aa109e..989eee0 100644
--- a/kc/core/cpu/exceptions.S
+++ b/kc/core/cpu/exceptions.S
@@ -15,7 +15,7 @@
ISR_STORE_CALLEE_REGS
.endm
-.macro EXCEPTION_END vec:req, code
+.macro EXCEPTION_END
// restore all the registers
ISR_RESTORE_CALLEE_REGS
ISR_RESTORE_CALLER_REGS
@@ -33,11 +33,7 @@
.endif
movq %rsp, %rdi
ISR_CALL \name\()_handler
- .if \vec > 9 && \vec < 15 || \vec == 17 || \vec == 21 || \vec > 28 && \vec < 31
- EXCEPTION_END \vec, 1
- .else
- EXCEPTION_END \vec
- .endif
+ EXCEPTION_END
.size \name\()_isr, . - \name\()_isr
.endm