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| author | Ada Christine <adachristine18@gmail.com> | 2022-02-24 16:48:53 +0000 |
|---|---|---|
| committer | Ada Christine <adachristine18@gmail.com> | 2022-02-24 16:48:53 +0000 |
| commit | 9fcd505ab3106e9fbf586e6d16e53e3e44936215 (patch) | |
| tree | add54829625e90c27a1c11a160e9deb5e5877ae1 /kc/core/cpu/exceptions.S | |
| parent | 1923e47fd296399180eaf19b990d5e951d71ccd2 (diff) | |
context struct for ISRs rather than using param registers; second-stage handlers should deal with that i think
Diffstat (limited to 'kc/core/cpu/exceptions.S')
| -rw-r--r-- | kc/core/cpu/exceptions.S | 21 |
1 files changed, 8 insertions, 13 deletions
diff --git a/kc/core/cpu/exceptions.S b/kc/core/cpu/exceptions.S index 087cf12..8aa109e 100644 --- a/kc/core/cpu/exceptions.S +++ b/kc/core/cpu/exceptions.S @@ -1,32 +1,26 @@ #include "exceptions.h" #include "interrupt.h" -.macro EXCEPTION_BEGIN vec:req, code=0 +.macro EXCEPTION_BEGIN vec:req, code // just in case something tried to be clever before - cld + pushq $\vec + .ifb \code + pushq $0 + .endif // push param registers ISR_STORE_PARAM_REGS - // store certain parameters - movb $\vec,%dil - .if \code - movq ISR_PARAM_REGS_SIZE(%rsp), %rsi - .else - xor %rsi, %rsi - .endif // caller-saved registers ISR_STORE_CALLER_REGS // callee-saved registers ISR_STORE_CALLEE_REGS .endm -.macro EXCEPTION_END vec:req, code=0 +.macro EXCEPTION_END vec:req, code // restore all the registers ISR_RESTORE_CALLEE_REGS ISR_RESTORE_CALLER_REGS ISR_RESTORE_PARAM_REGS - .if \code - add $8, %rsp - .endif + add $16, %rsp iretq .endm @@ -37,6 +31,7 @@ .else EXCEPTION_BEGIN \vec .endif + movq %rsp, %rdi ISR_CALL \name\()_handler .if \vec > 9 && \vec < 15 || \vec == 17 || \vec == 21 || \vec > 28 && \vec < 31 EXCEPTION_END \vec, 1 |